1. Field of the Invention
The present invention relates to a data transfer control device for controlling the data transfer between a plurality of PCI buses in a system comprising a plurality of PCI buses.
2. Description of the Related Art
A PCI (Peripheral Component Interconnect) bus is described in detail in the PCI Local Bus Specification, Rev. 2.1, for example. The PCI bus has a characteristic in that the address transfer and the data transfer are performed in 32 signal lines in time division multiplex. If transfer by multiplex is performed, data stored in the continuous address in the storage device of a peripheral device can be transferred to another peripheral device at high-speed. In data transfer via the PCI bus, it is essential to acquire an access right to the PCI bus, and a master device, which is always installed for the PCI bus, grants the access right to one of the plurality of devices connected to the PCI bus.
In this case, when a device connected to one PCI bus out of two PCI buses performs burst transfer to an external storage device connected to the data transfer control device, it is necessary to complete the next data transfer within 8 clock cycles after one data transfer is completed, so that the burst transfer is not interrupted.
However, as the timing chart depicting the operation of the data transfer control device in the prior art in FIG. 2 shows, memory access takes 5 clock cycles, so if access for a clock cycles to a target device is generated at the secondary PCI bus (hereafter S-PCI bus) side when the burst transfer, of which the data transfer interval is 5 clock cycles, is being executed at the primary PCI bus (hereafter P-PCI bus) side, it takes 10+α clock cycles, that is, S-PCI side transfer clock cycle α+P-PCI side memory access 5 clock cycles+P-PCI side transfer 5 clock cycles, from the completion of the previous data transfer to the completion of the data transfer of the P-PCI bus after memory access from the S-PCI bus. Therefore burst transfer may be interrupted since the 8 clock rule cannot be maintained, and access to both memories while following the 8 clock rule specified by the PCI bus cannot be arbitrated, so data cannot be transferred at high-speed.
It is an object of the present invention to implement high-speed data transfer even if access is generated at the S-PCI bus side during burst transfer at the P-PCI bus side.